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[VHDL-FPGA-Verilog] fir_lowpass

Description: 简易FIR低通滤波器的verilog代码-Simple FIR low-pass filter verilog code
Platform: | Size: 1024 | Author: 谢文斌 | Hits:

[VHDL-FPGA-Verilog] FIR_FILTER

Description: FIR滤波器的verilog实现，包含testbench，以及设计文档，文档里面详细介绍了滤波器系数的求取-FIR filter verilog implementation, including testbench, and the design document, the document which details the filter coefficients to strike
Platform: | Size: 14336 | Author: 雷 | Hits:

[VHDL-FPGA-Verilog] FIR_dida

Description: 自己写的FIR滤波器设计，verilog语言写的，很好用-Write your own FIR filter design, verilog language, easy to use
Platform: | Size: 1504256 | Author: chenshuo | Hits:

[Other Embeded program] FIRverilog

Description: 多种FIR滤波器的verilog语言实现 (数字信号处理的FPGA实现)-Verilog language variety FIR filter implementation (digital signal processing FPGA implementation)
Platform: | Size: 8192 | Author: 宋俊 | Hits:

[VHDL-FPGA-Verilog] 16QAM

Description: 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
Platform: | Size: 5120 | Author: nike | Hits:

[Other] fir4btp

Description: 4tap FIR filter in verilog code
Platform: | Size: 1024 | Author: pravat | Hits:

[VHDL-FPGA-Verilog] FILTER

Description: VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION -VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION
Platform: | Size: 1024 | Author: gsp | Hits:

[VHDL-FPGA-Verilog] 2D-FILTER

Description: VERILOG CODE FOR 2D FIR FILTER
Platform: | Size: 2048 | Author: gsp | Hits:

[VHDL-FPGA-Verilog] fir_verilog_matlab

Description: 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.
Platform: | Size: 1352704 | Author: 郭婷 | Hits:

[Other] Xilinx-FIRfilter-iP

Description: Xilinx IP核设计FIR滤波器,调用IP核实现FIR滤波器，相关具体步骤还有Verilog HDL的相关代码-verilog HDL
Platform: | Size: 346112 | Author: 陈旭 | Hits:

[LabView] code

Description: 用Verilog写的采用LSM算法的自适应性FIR滤波器，有testbench和主体代码，亲测可用-Written using Verilog LSM algorithm using adaptive FIR filters, and the body has testbench code, pro-test available
Platform: | Size: 6144 | Author: Mary | Hits:

[VHDL-FPGA-Verilog] fir16.v

Description: 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter
Platform: | Size: 1024 | Author: lijinpeng | Hits:

[VHDL-FPGA-Verilog] fir48

Description: 48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
Platform: | Size: 2048 | Author: lijinpeng | Hits:

[VHDL-FPGA-Verilog] 20140825

Description: FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
Platform: | Size: 5541888 | Author: lirui | Hits:

[VHDL-FPGA-Verilog] 1

Description: verilog编写的11阶FIR数字滤波器-The 11 order FIR digital filter Verilog prepared!!!!!!!!!!!!!!!!!!!!!
Platform: | Size: 681984 | Author: 网速卡 | Hits:

[Other] 8fir

Description: 这是一个verilog语言描述的8阶fir滤波器-8firFILTERdesign
Platform: | Size: 1024 | Author: 陈浩 | Hits:

[Other] low_pass-filter-design

Description: 基于Verilog的fir低通数字滤波器-Verilog-based fir low pass digital filter
Platform: | Size: 719872 | Author: SamHillzj | Hits:

[Other Embeded program] FIR32

Description: 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
Platform: | Size: 3072 | Author: Awei | Hits:

[Other] filter

Description: 大神写的FIR滤波器，verilog所写，短小精悍，易读懂！-Great God wrote the FIR filter, verilog written, short and pithy, easy to read!
Platform: | Size: 521216 | Author: 邓小林 | Hits:

[VHDL-FPGA-Verilog] firfilterverilog

Description: FIR FILTER DESIGNED IN VERILOG FOR 4 BIT MULTIPLIER
Platform: | Size: 143360 | Author: neha | Hits:
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